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CD4021BE CD4021 CMOS 8-Stage Static Shift Register Breadboard-Friendly IC (Pack of 20)

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$23.09

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  • Medium speed operation…12 MHz (typ.) clock rate at VDD – VSS = 10 V, 5-V, 10-V, and 15-V parametric ratings
  • Fully static operation, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 8 master-slave flip-flops plus output buffering and control gating, Applications: Parallel input/serial output data queueing Parallel to serial data conversion General-purpose register
  • 100% tested for quiescent current at 20 V, Standardized, symmetrical output characteristics, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Noise margin (full package-temperature range) = 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V


The CD4021B are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. Entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.